The present invention relates to a semiconductor device, an electrical device system including the semiconductor device, and a method of producing the semiconductor device.
Patent Reference has disclosed a conventional semiconductor device, in which a photodiode sensor and a control circuit transistor are formed on a semiconductor substrate with an insulation film in between.
Patent Reference: Japanese Patent Publication No. 2010-232555
An example of the conventional semiconductor device will be explained with reference to FIGS. 14 and 15. FIG. 14 is a schematic plan view showing an example of a configuration of a conventional semiconductor device 900. FIG. 15 is a schematic sectional view showing the example of the configuration of the conventional semiconductor device 900. The conventional semiconductor device 900 includes a diode 905 and a MOS-type transistor 904 formed on an SOI (Silicon On Insulation) substrate. The conventional semiconductor device 900 is configured to function as a sensor for detecting an X-ray and the like.
As shown in FIG. 14, in a plan view showing the configuration of the conventional semiconductor device 900, a substrate contact portion 902 is arranged on a periphery of the conventional semiconductor device 900, and a circuit element region 903 including a sensor is disposed inside the substrate contact portion 902. It should be noted that the substrate contact portion 902 includes N-type drawing out electrode regions 910 and 911 (described later) and electrodes 920 and 921 (described later) connected to the N-type drawing electrode regions 910 and 911, respectively. In FIG. 14, an electrode with a ring shape including the electrode 920 and 921 is shown as a part of the substrate contact portion 902.
As shown in FIG. 15, the conventional semiconductor device 900 includes the SOI substrate including an N-type semiconductor layer 907, an embedded oxide film 909, and a P-type semiconductor layer 908. Further, the MOS-type transistor 904 and the like are disposed in the P-type semiconductor layer 908 in the embedded oxide film 909 for performing a circuit operation. Further, the diode 905 as the sensor is formed in the N-type semiconductor layer 907 arranged below the embedded oxide film 909. It should be noted that the diode 905 may be referred to as a pixel, and the configuration including a periphery circuit element having the MOS-type transistor 904, a resistor, a capacitor, and the like; the diode 905 (a plural in general); and the like may be referred to as a single pixel circuit (a single pixel circuit 906 in FIG. 15). As described above, the conventional semiconductor device 900 has the configuration, in which the periphery circuit element and the sensor are integrated on one single substrate.
Further, as shown in FIG. 15, in the vertical sectional view showing the configuration of the substrate contact portion 902, the substrate contact portion 902 includes the N-type drawing electrode regions 910 and 911 and the electrodes 920 and 921 connected to the N-type drawing out electrode regions 910 and 911, respectively. A positive potential of a power source 904 is connected to the electrodes 920 and 921. The diode 905 includes a P-type drawing out electrode region 912 and an electrode 922 connected to the P-type drawing electrode regions 912. A negative potential of the power source 904 is grounded (GND) and connected to the electrode 922.
In the conventional semiconductor device 900 described above, the positive potential of the power source 924 is connected also to a bottom surface of the N-type semiconductor layer 907 (a surface opposite to the surface where the embedded oxide film 909 is formed) through an electrode (not shown). When the power source 924 applies a reverse bias of a few hundred volt to a PN connection (a junction) formed with the P-type drawing out electrode region 912 and the N-type semiconductor layer 907, a depletion layer spreads in the N-type semiconductor layer 907, thereby increasing detection sensitivity when an X-ray and the like is incidents on the conventional semiconductor device 900.
Further, when the power source 924 applies the reverse bias to the PN connection, the substrate contact portion 902 applies a bias to the N-type semiconductor layer 907, so that the substrate contact portion 902 restricts the depletion layer from spreading. More specifically, the N-type drawing out electrode regions 910 and 911 have an N-type impurity having a concentration greater than a concentration of the N-type impurity in the N-type semiconductor layer 907. Accordingly, the spreading of the depletion layer is restricted in the N-type drawing electrode regions 910 and 911. As a result, the substrate contact portion 902 also functions as a guard ring for preventing the depletion layer from reaching an edge surface of the conventional semiconductor device 900 after pelletizing (cutting into a chip piece).
In general, it is difficult to use a collection lens or a collection mirror in the X-ray sensor due to the fact that an X-ray has a small reflective index variance or a small reflection rate. Accordingly, in the X-ray sensor, it is possible to use only a simple optical system. As a result, it is necessary to provide the X-ray sensor with a large area for capturing a large image, so that the circuit element region 903 tends to be enlarged.
As described above, in the conventional semiconductor device 900, an N-type substrate contact portion having the same polarity as that of the N-type semiconductor layer 907 is not disposed in the substrate contact portion 902. Accordingly, especially when the area of the circuit element region 903 is increased to enlarge the area of the sensor, it is difficult to secure an escaping path of charges of plasma generated during a plasma etching process when a contact hole and a laminated metal are etched through the plasma etching process when a multilayer wiring portion is formed. Further, it is difficult to secure an escaping path of a surge electrical current. Accordingly, if arc discharge occurs during a via (a through electrode) forming step or a metal etching step in a wafer manufacturing process, it is difficult to secure the escaping path of the surge electrical current, and a significant damage may be occurred in a wafer.
To this end, the N-type substrate contact portion may be disposed in the circuit element region 903, so that the N-type substrate contact portion functions as the escaping path of charges of the plasma. However, when the potential of the N-type substrate contact portion is fixed to the ground potential, the N-type substrate contact portion is connected to the substrate contact portion 902 having the N-type drawing out electrode region 910 and the N-type drawing out electrode region 911 through the N-type semiconductor layer 907. Accordingly, an unnecessary electrical current may be generated from the substrate contact portion 902, to which the power source 924 applies the positive potential, to the N-type substrate contact portion thus grounded.
Further, when the positive potential of the power source 924 is connected to the N-type substrate contact portion to apply the positive bias thereto, a breakdown may occur between the P-type drawing out electrode region 912 and the N-type substrate contact portion when the depletion layer of the PN connection formed with the P-type drawing out electrode region 912 and the N-type semiconductor layer 907 reaches the N-type substrate contact portion. Accordingly, an unnecessary electrical current may be generated. For the reasons described above, it is difficult to apply the potential to the N-type substrate contact portion.
Further, when the PN connection formed with the P-type drawing out electrode region 912 and the N-type semiconductor layer 907 has a low voltage tolerance, it may be possible to flow charges through the breakdown of the PN connection when charges of the plasma flow through during the plasma etching process. However, the N-type semiconductor layer 907 is formed of a substrate having a high voltage tolerance, so that the entire portion of the N-type semiconductor layer 907 can become the depletion layer. Accordingly, the PN connection formed with the P-type drawing out electrode region 912 and the N-type semiconductor layer 907 tends to have a high voltage tolerance of, for example, a few thousands volts. Accordingly, it is difficult to utilize the PN connection formed with the P-type drawing out electrode region 912 and the N-type semiconductor layer 907 as the escaping path of charges.
In view of the problems described above, an object of the present invention is to provide a semiconductor device, an electrical device system including the semiconductor device, and a method of producing the semiconductor device capable of solving the problems of the conventional electrical device. In the present invention, it is possible to prevent damage caused by an external charge while suppressing an unnecessary leak electrical current.
Further objects and advantages of the invention will be apparent from the following description of the invention.